Testing apparatus for testing a device under test and comparator circuit and calibration apparatus for the testing apparatus

ABSTRACT

There is provided a testing apparatus for testing a device under test, wherein the testing apparatus is provided with a timing generator for generating a timing signal indicating the timing at which a test signal is applied; a plurality of timing delay units for delaying the timing signal; a plurality of drivers for applying the delayed test signals; a sampler for sampling the test signal and outputting a sample voltage; a comparator for outputting a comparison result indicating whether the sample voltage is higher than the reference voltage; a determination part for determining whether the sample voltage matches the reference voltage; and a timing calibration part for calibrating the delay time caused in the timing signal by the plurality of timing delay units in order to synchronize the timing at which the test signals are applied to the device under test.

TECHNICAL FIELD

The present invention relates to a comparator circuit, a calibrationapparatus, a testing apparatus, and a calibration method. The presentinvention particularly relates to a calibration apparatus forcalibrating the output timing of a test signal applied to a device undertest; a testing apparatus; a calibration method; and a comparatorcircuit for implementing the aforementioned devices and method.

BACKGROUND ART

A testing apparatus has conventionally been used for applying a testsignal to a device under test in the case of semiconductor devicetesting. When the device being tested by this testing apparatus isprovided with a plurality of terminals, it is sometimes necessary forthe test signal to be applied to each of the plurality of terminals at aconsistent timing.

FIG. 1 shows an example of the structure of the testing apparatus 10according to the background art of the present invention. The testingapparatus 10 performs testing of the DUT (Device Under Test: devicebeing tested) 130 by applying a test signal to each of a plurality ofterminals of the DUT 130. The testing apparatus 10 is provided with atiming generator 100, a plurality of test boards 110, and a plurality oftransmission channels 120. The timing generator 100 generates a timingsignal indicating the timing at which the test signal is applied to theDUT 130, and feeds the timing signal to each of the plurality of testboards 110. Each of the plurality of test boards 110 is provided so asto correspond to one of the plurality of terminals of the DUT 130, andhas a timing delay unit 112 for delaying the timing signal generated bythe timing generator 100, and a driver 114 for applying the test signalto corresponding one of the terminals of the DUT 130 via a transmissionchannel 120 at the timing indicated by the timing signal thus delayed.

The plurality of drivers 114 each have varying characteristics, andsince the transmission channel length is not necessarily the same ineach of the plurality of transmission channels 120, there is sometimesvariation in the timing at which the test signals are applied to the DUT130 by the plurality of drivers 114. Therefore, the waveform of the testsignal applied to the DUT 130 by each of the plurality of drivers 114 isobserved using an oscilloscope on the point nearest to the DUT 130. Thetiming at which the test signal is applied to the DUT 130 by each of theplurality of drivers 114 is synchronized based on the observed waveformby calibrating the delay time caused in the timing signal by theplurality of timing delay units 112.

FIG. 2 shows the structure of a testing apparatus 20 according to thebackground art of the present invention. The testing apparatus 20performs testing of the DUT by applying a test signal to each of aplurality of terminals of the DUT. The testing apparatus 20 is providedwith a timing generator 200, a plurality of test boards 210, a pluralityof transmission channels 215, and a calibration apparatus 220. Thetiming generator 200 generates a timing signal indicating the timing atwhich the test signal is applied to the DUT, and feeds the timing signalto each of the plurality of test boards 210. The timing generator 200also generates a strobe signal and feeds the strobe signal to thecalibration apparatus 220. Each of the plurality of test boards 210 isprovided so as to correspond to one of the plurality of terminals of theDUT, and has a timing delay unit 212 for delaying the timing signalgenerated by the timing generator 200, and a driver 214 for applying thetest signal to corresponding one of the terminals via a transmissionchannel 215 at the timing indicated by the timing signal thus delayed.

The calibration apparatus 220 has a comparator 222, a determination part224, and a timing calibration part 226. The comparator 222 acquires inplace of the DUT the test signal outputted by each of the plurality ofdrivers 214, compares the test signal thus acquired with a referencevoltage V_(REF), and outputs the comparison result to the determinationpart 224. The determination part 224 detects the comparison resultoutputted by the comparator 222 at the timing indicated by the strobesignal generated by the timing generator 200, and determines whether thevoltage of the test signal matches the reference voltage V_(REF) at thattiming. The timing calibration part 226 synchronizes the timing at whichthe test signal is applied to the DUT by each of the plurality ofdrivers 214, by calibrating the test signals applied to the DUT by eachof the plurality of drivers 214 by calibrating the delay time caused inthe timing signal by the plurality of timing delay units 212, based onthe timing at which it is determined in the determination part 224 thatthe voltage of the test signal matches the reference voltage V_(REF).

Drawbacks are known to occur in the conventional testing apparatus fortesting a DUT by applying test signals to the DUT whereby the highfrequency components of the test signals are attenuated by resistance inthe transmission channels and other effects, and test signals havingwaveforms different from desired waveforms are applied to the DUT.Techniques have been proposed for overcoming these drawbacks by using anoscilloscope to acquire waveforms of the test signals outputted by thetesting apparatus and correcting the waveforms of the test signals basedon the acquired waveforms (see the specification of International PatentApplication Laid Open No. 03/044550, for example).

DISCLOSURE OF THE INVENTION

Problem to be Solved by the Invention

The calibration method described in FIG. 1 has drawbacks wherebyefficient calibration is difficult to perform because of the need for anexpensive oscilloscope and a long time for calibration. The calibrationmethod described in FIG. 2 has drawbacks whereby the effects onequivalent rise time due to bandwidth inadequacy of the comparator 222with the increase in frequency of the test signal, or the effects onfluctuations in the response time of the comparator 222 according to theoverdrive voltage make high-precision calibration difficult to perform.The testing apparatus described in International Patent Application LaidOpen No. 03/044550 also has drawbacks in that an expensive oscilloscopeis required for acquiring waveforms of the test signals applied to theDUT.

Therefore, an object of the present invention is to provide a comparatorcircuit, a calibration apparatus, a testing apparatus, and a calibrationmethod capable of overcoming the abovementioned drawbacks. This objectis achieved by the combination of characteristics described in theindependent claims. The dependent claims specify an even more usefulspecific example of the present invention.

Means for Solving the Above-Mentioned Problems

A first embodiment of the present invention is a comparator circuit forcomparing an analog measured signal with an analog reference signal andoutputting the comparison result, wherein the comparator circuit isprovided with a sampler for sampling the measured signal at apredetermined timing and outputting a sample voltage of the measuredsignal; and a comparator for comparing the sample voltage with thereference voltage and outputting the comparison result indicatingwhether the sample voltage is higher than the reference voltage. Thesampler may have a switching circuit and a capacitor, wherein theswitching circuit applies the measured signal to the capacitor at thepredetermined timing and the comparator compares the voltage applied andcharged into the capacitor with the reference voltage as the samplevoltage. The sampler may be provided with a noise extraction circuit forextracting noise superimposed on a sampling pulse; the noise extractedby the noise extraction circuit is subtracted from the sample voltage byan analog subtraction circuit; and the noise superimposed on the samplevoltage is removed and compared with the reference voltage. Thecomparator may have a sample voltage transistor for amplifying thesample voltage; a reference voltage transistor for amplifying thereference voltage; and a comparison result output part for comparing theamplified sample voltage with the amplified reference voltage andoutputting a comparison result indicating whether the amplified samplevoltage is higher than the amplified reference voltage.

A second embodiment of the present invention is a calibration apparatusfor acquiring an analog measured signal outputted by a driver andcalibrating the output timing of the measured signal from the driver,wherein the calibration apparatus is provided with a sampler forsampling the measured signal at a predetermined timing and outputting asample voltage of the measured signal; a comparator for comparing thesample voltage with an analog reference voltage and outputting acomparison result indicating whether the sample voltage is higher thanthe reference voltage; a determination part for determining that thesample voltage matches the reference voltage at a timing at which thecomparison result changes as the timing of sampling is continuouslychanged by the sampler; and a timing calibration part for calibratingthe output timing of the measured signal from the driver based on thetiming at which it is determined in the determination part that thesample voltage matches the reference voltage.

A third embodiment of the present invention is a testing apparatus fortesting a device under test; wherein the testing apparatus is providedwith a timing generator for generating a timing signal indicating thetiming at which a test signal is applied to each of a plurality ofterminals provided to the device under test; a plurality of timing delayunits for delaying each timing signal; a plurality of drivers providedso as to correspond with each of the plurality of timing delay units,for applying the test signal to each of the plurality of terminals atthe timing indicated by each of the timing signals delayed by each ofthe plurality of timing delay units; a sampler for sampling the testsignal outputted by the corresponding driver for each of the pluralityof drivers at a predetermined timing, and outputting a sample voltage ofthe test signal; a comparator for comparing the sample voltage with ananalog reference voltage and outputting a comparison result indicatingwhether the sample voltage is higher than the reference voltage; adetermination part for determining that the sample voltage matches thereference voltage at a timing at which the comparison result changes asthe timing of sampling is continuously varied by the sampler; and atiming calibration part for calibrating the delay time caused in thetiming signal by at least one of the plurality of timing delay unitsbased on the timing at which it is determined in the determination partthat the sample voltage matches the reference voltage for each of theplurality of drivers in order to synchronize the timing at which thetest signal outputted by each of the plurality of drivers is applied tothe device under test.

The timing generator may also generate a strobe signal in relation tothe timing signal, for indicating the timing at which the samplersamples, and the timing at which the determination part detects thecomparison results. The testing apparatus may also be provided with afrequency divider for frequency-dividing the strobe signal; and a strobedelay unit for delaying the strobe signal frequency-divided in thefrequency divider; wherein the determination part determines that thesample voltage matches the reference voltage in the delay time by whichthe comparison result is changed when the delay time by which the strobedelay unit delays the strobe signal is changed; and the timingcalibration part calibrates the delay time caused in the timing signalby at least one of the plurality of timing delay units based on thedelay time of the strobe signal at which it is determined in thedetermination part that the sample voltage matches the reference voltagefor each of the plurality of drivers in order to synchronize the timingat which the test signal outputted by each of the plurality of driversis applied to the device under test.

The testing apparatus may be provided with a reference voltagecontroller for continuously changing the reference voltage with whichthe comparator compares the sample voltage of the test signal, in orderto acquire a voltage at the timing indicated by the delayed strobesignal in the test signal outputted by each of the plurality of drivers;and a waveform acquisition part for acquiring the waveform of the testsignal outputted by each of the plurality of drivers, by continuouslychanging the delay time for delaying the strobe signal by the strobedelay unit, and by continuously changing the reference voltage by thereference voltage controller. The testing apparatus may also be providedwith a test signal correction part for correcting the signal outputtedby the driver so that the desired the test signal is applied to thedevice under test based on the waveform of the test signal outputted byeach of the plurality of drivers acquired by the waveform acquisitionpart.

A fourth embodiment of the present invention is a calibration method foracquiring the test signal outputted by each of a plurality of driversprovided in a testing apparatus for testing a device under test andcalibrating the output timing of the test signal from each of theplurality of drivers; wherein the calibration method includes a timinggeneration step for generating a timing signal indicating the timing atwhich the test signal is applied to each of a plurality of terminals ofthe device under test; a timing delay step for delaying each timingsignal and outputting a plurality of delayed timing signals; a testsignal outputting step whereby the plurality of drivers each output thetest signal at the timing indicated by each of the plurality of delayedtiming signals; a sampling step for sampling at a predetermined timingthe analog test signal outputted by the driver and outputting the samplevoltage of the test signal for each of the plurality of drivers; acomparison step for comparing the sample voltage with an analogreference voltage and outputting comparison results indicating whetherthe sample voltage is higher than the reference voltage; a determinationstep for determining that the sample voltage matches the referencevoltage when the comparison result changes as the timing at which thetest signal is sampled in the sampling step is continuously varied; anda timing calibration step for calibrating the delay time caused in thetiming signal by at least one of the plurality of timing delay unitsprovided so as to correspond to each of the plurality of drivers, basedon the timing at which it is determined in the determination step thatthe sample voltage matches the reference voltage for each of theplurality of drivers in order to synchronize the timing at which thetest signal outputted by each of the plurality of drivers is applied tothe device under test.

A fifth embodiment of the present invention is a testing apparatus fortesting a device under test; wherein the testing apparatus is providedwith a driver for applying a test signal to the device under test; asampler for sampling at a predetermined timing the analog output signaloutputted from the device under test and outputting a sample voltage ofthe output signal in relation to the test signal applied by the driverto the device under test; and a comparator for comparing the samplevoltage with an analog reference voltage and outputting a comparisonresult indicating whether the sample voltage is higher than thereference voltage.

The summary of the present invention given above does not enumerate allof the necessary characteristics of the present invention, andsub-combinations of these characteristics are also encompassed by thepresent invention.

Effect of The Invention

By the present invention, calibration of the timing at which a testsignal is applied to a device under test can be performed with highprecision without the use of an expensive oscilloscope.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an example of the structure of thetesting apparatus 10 according to the background art of the presentinvention;

FIG. 2 is a block diagram showing an example of the structure of thetesting apparatus 20 according to the background art of the presentinvention;

FIG. 3 is a block diagram showing an example of the overall structure ofthe testing apparatus 30 according to a first embodiment of the presentinvention;

FIG. 4 is a waveform diagram for describing the operation of thewaveform acquisition part 368 shown in FIG. 3;

FIG. 5 is a waveform diagram showing an example of the relationshipbetween the test signal and the strobe signal;

FIG. 6 is waveform diagram showing an example of the relationshipbetween the strobe signal and the sample voltage;

FIG. 7 is a waveform diagram showing an example of the relationshipbetween the sample voltage and the comparison results in the comparator350;

FIG. 8 is a waveform diagram showing an example of the relationshipbetween the desired waveform 600 of the test signal and the waveform 630of the test signal corrected by the test signal correction part 370;

FIG. 9 is a connection diagram showing an example of the structure ofthe sampler 348;

FIG. 10 is a connection diagram for describing a working example of asampler having the noise removal capability of the present invention;

FIG. 11 is a waveform diagram for describing the operation of thesampler having noise removal capability shown in FIG. 10;

FIG. 12 is a connection diagram for describing another working exampleof the sampler having noise removal capability shown in FIG. 10;

FIG. 13 is a connection diagram for describing another working exampleof the sampler having noise removal capability shown in FIG. 10;

FIG. 14 is a connection diagram for describing yet another workingexample of the sampler having noise removal capability shown in FIG. 10;

FIG. 15 is a connection diagram for describing yet another workingexample of the sampler having noise removal capability shown in FIG. 10;

FIG. 16 is a connection diagram for describing yet another workingexample of the sampler having noise removal capability shown in FIG. 10;

FIG. 17 is a connection diagram showing an example of the structure ofthe comparator 350;

FIG. 18 is a block diagram showing an example of the structure of thecalibration apparatus according to a modification of the firstembodiment of the present invention;

FIG. 19 is a block diagram showing an example of the structure of thesample voltage in the calibration apparatus according to a modificationof the first embodiment of the present invention; and

FIG. 20 is a block diagram showing an example of the overall structureof the testing apparatus according to a second embodiment of the presentinvention.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described hereinafter, butthe embodiments described below in no way limit the present invention asdefined in the claims, and not necessarily all combinations ofcharacteristics described in these embodiments are essential forachieving the objects of the present invention.

FIG. 3 shows an example of the overall structure of the testingapparatus 30 according to a first embodiment of the present invention.The testing apparatus 30 generates a test signal and applies the testsignal to the DUT, compares with an expected value the output signaloutputted as a result of the operation of the DUT based on the testsignal, and determines the quality of the DUT. In the testing apparatus30 according to the present embodiment, the calibration apparatus 340acquires in place of the DUT the test signals generated and outputted bya plurality of test boards 320. The calibration apparatus 340 performscalibration for the output timing of the test signal in each of theplurality of test boards 320 for applying the test signal to each of aplurality of terminals of the DUT, based on the results of sampling theacquired test signal and comparing the test signal with a referencevoltage. The purpose of this configuration is for the plurality testboards 320 to synchronize the timing at which the test signal is appliedto each of the plurality of terminals, and to perform high-precisiontesting of the DUT.

The testing apparatus 30 is provided with a timing generator 300, aplurality of test boards 320, a plurality of transmission channels 330,a frequency divider 360, a strobe delay unit 362, a delay controller364, a calibration apparatus 340, a reference voltage controller 366, awaveform acquisition part 368, and a test signal correction part 370.The timing generator 300 generates a timing signal indicating the timingat which the test signal is applied to each of the plurality ofterminals of the DUT, and feeds the timing signal to each of theplurality of test boards 320. The timing generator 300 also generatesand feeds to the calibration apparatus 340 a strobe signal in relationto the timing signal, for indicating the timing at which the test signalis sampled in the calibration apparatus 340, and the timing at which theresult of comparison with the reference voltage is detected.

Each of the plurality of test boards 320 is provided so as to correspondto one of the plurality of terminals of the DUT, and has a timing delayunit 322 and a driver 324. The timing delay unit 322 delays the timingsignal generated by the timing generator 300, and outputs the delayedtiming signal to the driver 324. The driver 324 applies the test signalvia a transmission channel 330 to the terminal corresponding to the testboard 320 having the driver 324 at the timing indicated by the timingsignal delayed by the timing delay unit 322.

The frequency divider 360 frequency-divides the strobe signal outputtedby the timing generator 300, and outputs the frequency-divided signal tothe strobe delay unit 362. The strobe delay unit 362 delays the strobesignal frequency-divided in the frequency divider 360, and outputs theresult to the calibration apparatus 340. The delay controller 364 setsthe delay time of the strobe signal in the strobe delay unit 362, andnotifies the calibration apparatus 340 and the waveform acquisition part368 of the delay time thus set.

The calibration apparatus 340 acquires in place of the DUT the analogtest signal outputted by each of the plurality of drivers 324, andcalibrates the output timing of the test signals from each of theplurality of drivers 324 based on the test signal thus acquired. Thecalibration apparatus 340 has a comparator circuit 342, a determinationpart 344, and a timing calibration part 346. The comparator circuit 342includes a sampler 348 and a comparator 350, compares the analog testsignal (measured signal) outputted by each of the plurality of drivers324 with an analog reference voltage, and outputs the comparison result.

The sampler 348 samples the analog test signal outputted by the driver324 for each of the plurality of drivers 324 at a predetermined timing,and outputs the sample voltage of the test signal to the comparator 350.Specifically, the sampler 348 samples the test signal at the timingindicated by the strobe signal that is frequency-divided in thefrequency divider 360 and delayed in the strobe delay unit 362. Thecomparator 350 compares the analog sample voltage outputted by thesampler 348 with an analog reference voltage, and outputs to thedetermination part 344 the comparison result indicating whether thesample voltage is higher than the reference voltage. Specifically, thecomparator 350 outputs the logical value “1” as the comparison result tothe determination part 344 when the analog sample voltage is higher thanthe analog reference voltage, and outputs the logical value “0” when theanalog sample voltage is lower than the analog reference voltage.

The determination part 344 detects the comparison result outputted bythe comparator 350 at a timing based on the timing at which the sampler348 samples the test signal. The determination part 344 determines thatthe sample voltage matches the reference voltage at a timing when thedetected comparison result changes as the timing at which the sampler348 samples the test signal is continuously varied, and outputs thedetermination result to the timing calibration part 346 and the waveformacquisition part 368. Specifically, the determination part 344 detectsthe comparison result at a timing based on the delayed strobe signal,and determines that the sample voltage matches the reference voltage ata delay time where the comparison result changes as the delay controller364 continuously varies the delay time of the strobe signal set in thestrobe delay unit 362.

The timing calibration part 346 calibrates the delay time caused in thetiming signal by at least one of the plurality of timing delay units 322based on the timing at which it is determined in the determination part344 that the sample voltage matches the reference voltage for each ofthe plurality of drivers 324 in order to synchronize the timing at whichthe test signal outputted by each of the plurality of drivers 324 isapplied to the DUT. Specifically, the timing calibration part 346calibrates the delay time caused in the timing signal by at least one ofthe plurality of timing delay units 322 based on the delay time of thestrobe signal acknowledged by the delay controller 364 when it isdetermined in the determination part 344 that the sample voltage matchesthe reference voltage for each of the plurality of drivers 324.

The reference voltage controller 366 continuously changes the referencevoltage with which the comparator 350 compares the sample voltage of thetest signal, in order to acquire a voltage at the timing indicated bythe delayed strobe signal in the test signal outputted by each of theplurality of drivers 324. The waveform acquisition part 368 plots thewaveform of the test signal outputted by each of the plurality ofdrivers 324 and acquires data for a plurality of plotted points, by thedelay controller 364 continuously changing the delay time by which thestrobe signal is delayed by the strobe delay unit 362, and the referencevoltage controller 366 continuously changing the reference voltage, andoutputs the point data to the test signal correction part 370.

FIG. 4 shows the manner in which the point data for plotting thewaveform of the test signal are acquired. In this arrangement, thesubstantial midpoint of the rise time of the test signal is set as thereference phase, the test signal is sampled while the delay time isoffset in the sequence t1, t2, t3, . . . from this reference phase, thesampled voltage is found in relation to the reference voltage V_(REF),the voltage of the test signal at each delay time t1, t2, t3, . . . isplotted, and at least one period of the test signal is recorded. Thewaveform acquisition part 368 can draw the waveform of the test signalbased on the data thus acquired for indicating the points on thewaveforms of the plurality of test signals.

By adjusting resistance in the transmission channels 330, for example,the test signal correction part 370 corrects the signal outputted byeach of the plurality of drivers 324 on the basis of the waveform of thetest signal outputted by each of the plurality of drivers 324 andacquired by the waveform acquisition part 368. The test signalcorrection part 370 may, for example, correct the waveform of the testsignal inputted to the drivers 324 from a waveform shaper or othercircuit provided in each test board 320. Alternatively, the test signalcorrection part 370 may correct the waveform of the test signaloutputted by each driver 324. In yet another alternative, the testsignal correction part 370 may correct the waveform of the test signalinside each driver 324.

By the testing apparatus 30 according to the present embodiment, thecalibration apparatus 340 can calibrate the timing of the plurality oftiming delay units 322 based on the timing at which the test signal isapplied to the DUT by each of the plurality of drivers 324. The testingapparatus 30 can thereby test the DUT without the use of an expensiveoscilloscope.

By the testing apparatus 30 according to the present embodiment, thewaveform acquisition part 368 can precisely acquire the waveform of thetest signal outputted by each of the plurality of drivers 324. The testsignal correction part 370 can also correct the waveform of the testsignal outputted by each of the plurality of drivers 324 based on thewaveform of the test signal thus acquired. The testing apparatus 30 canthereby apply a test signal having a more correct waveform to the DUTand test the DUT with high precision.

FIG. 5 shows an example of the relationship between the test signal andthe strobe signal. FIG. 5A shows an example of the waveform of the testsignal (signal to be measured) inputted to the sampler 348. The timinggenerator 300 generates a strobe signal in relation to the timing signalindicating the timing at which the driver 324 applies the test signal tothe DUT. For example, the timing generator 300 may generate a strobesignal that has a pulse at the substantial midpoint of the rise time ofthe test signal outputted based on the timing signal, so that the periodof the pulse becomes the same as the period 400 in the test signal.

FIG. 5B shows an example of the waveform of the frequency-divided strobesignal. The frequency divider 360 frequency-divides the period of thepulses of the strobe signal generated by the timing generator 300 sothat the period may become an integer multiple of the period 400 of thetest signal, for example, the period 410, and outputs the result to thestrobe delay unit 362. The strobe delay unit 362 delays the strobesignal frequency-divided by the frequency divider 360 based on the delaytime set by the delay controller 364. The strobe delay unit 362 may useeither a positive or negative delay time, as indicated by the delay time420, for example.

FIG. 6 shows an example of the relationship between the strobe signaland the sample voltage. FIG. 6A shows an example of the strobe signal.FIGS. 6B and 6C show examples of the sample voltages of the strobesignal shown in FIG. 6A. The sampler 348 applies the sample voltage to acapacitor, whereby the capacitor is charged with the sample voltage, anddischarges the entire charged amount over a period of time indicated bythe discharge time determined by the discharge time constant in thesampler 348. When the discharge time is shorter than the period of thestrobe signal, the sampler 348 discharges the entire sample voltagecharged in one sampling by the time the next sampling is executed.Consequently, when the sample voltage must be evaluated for eachsampling, as with jitter measurement in the test signal, for example,the sampler 348 can output the appropriate sample voltage by setting thefrequency dividing number in the frequency divider 360 so that theperiod of the strobe signal becomes longer than the discharge time.

When the discharge time is longer than the period of the strobe signal,the sampler 348 amplifies the sample voltage by repeating sampling on aportion of the sample voltage even remained in the next sampling. Theamplified sample voltage reaches equilibrium in a voltage valuedetermined by the charge time constant and discharge time constant inthe sampler 348. The sampler 348 generally outputs a sample voltage thatis low with respect to the voltage of the inputted test signal in asingle sampling. Specifically, the sampler 348 outputs a sample voltagethat is 1/10^(th) to 1/100^(th) the voltage of the inputted test signalin a single sampling. Consequently, the sampler 348 can output a samplevoltage that is detectable by the comparator 350 by setting thefrequency division number in the frequency divider 360 so that theperiod of the strobe signal is shorter than the discharge time, andamplifying the sample voltage when the sample voltage outputted in asingle sampling is low with respect to the voltage that can be detectedby the comparator 350.

FIG. 7 shows an example of the relationship between the sample voltageand the comparison result of the comparator 350. FIG. 7A shows anexample of the waveform of the test signal inputted to the sampler 348.The sampler 348 outputs the sample voltage as the reference voltageV_(REF) when the reference voltage V_(REF)′ in application to the DUT issampled as the test signal.

FIG. 7B shows an example of the waveform that is the composite of thewaveforms of strobe signals generated at different timings. FIG. 7Cshows an example of the sample voltage that corresponds to each of thedifferent strobe signals. The sampler 348 outputs a sample voltage 530that is below the reference voltage V_(REF) when the test signal issampled at the timing indicated by the strobe signal 500. When the testsignal is sampled at the timing indicated by the strobe signal 510, thesampler 348 outputs a sample voltage 540 that matches the referencevoltage V_(REF). The sampler 348 outputs a sample voltage 550 that isabove the reference voltage V_(REF) when the test signal is sampled atthe timing indicated by the strobe signal 520.

FIG. 7D shows an example of the change in the comparison result in thecomparator 350 detected by the determination part 344 when the delaytime in the strobe signal is changed. The determination part 344 outputsthe comparison result as the logical value “0” in the timing based onthe strobe signal (strobe signal 500, for example) outputted by a samplevoltage that is lower than the sample voltage 540. The determinationpart 344 outputs the comparison result as the logical value “1” in thetiming based on the strobe signal (strobe signal 520, for example)outputted by a sample voltage that is higher than the sample voltage540. In other words, the comparison result detected by the determinationpart 344 varies near the delay time in the strobe signal 510corresponding to the sample voltage 540 that matches the referencevoltage V_(REF). Therefore, when the delay controller 364 continuouslyvaries the delay time of the strobe signal, the determination part 344determines that the voltage of the test signal inputted to the sampler348 matches the reference voltage V_(REF)′ in application to the DUT inthe delay time in which the comparison result in the comparator 350,detected at the timing indicated by the delayed strobe signal, changes.

The timing calibration part 346 calibrates the delay time caused in thetiming signal in the timing delay unit 322 corresponding to the driver324 that outputted the test signal, based on the timing at which it isdetected in the determination part 344 that the voltage of the testsignal matches the reference voltage V_(REF)′, and synchronizes thetiming at which the voltage of the test signal applied to the DUT byeach of the plurality of drivers 324 reaches the reference voltageV_(REF)′. The timing calibration part 346 selects a single driver 324from among the plurality of drivers 324, and calibrates the delay timeof the timing delay unit 322 corresponding to each of the plurality ofother drivers 324 so as to synchronize the timing of application of thetest signal by each of the plurality of other drivers 324 with thetiming of test signal application in the selected driver 324. In analternate configuration, the timing calibration part 346 calibrates thedelay time of the timing delay unit 322 corresponding to each of theplurality of drivers 324 so as to synchronize the timing of applicationof the test signal in each of the plurality of drivers 324 with apredetermined timing.

By the testing apparatus 30 according to the present embodiment, thetiming at which the voltage of the test signal matches the referencevoltage can be reliably detected by detecting the change in the resultof comparison between the sample voltage and the reference voltage whilethe delay time of the strobe signal is continuously varied. Thecalibration apparatus 340 can thereby calibrate the timing at which thetest signal is applied to the DUT with higher precision.

FIG. 8 shows an example of the relationship between the desired waveform600 of the test signal and the waveform 630 of the test signal correctedby the test signal correction part 370. The waveform 600 is the desiredwaveform of the test signal applied to the DUT. Even when the waveformof the test signal outputted by the driver 324 is the same as thewaveform 600 immediately after being outputted, the high frequencycomponents thereof can be attenuated by resistance in the transmissionchannels 330 and other effects, for example, and the waveform can bedifferent from the waveform 600 immediately before being applied to theDUT. The test signal correction part 370 corrects the test signaloutputted by the driver 324 so that the waveform of the test signalapplied to the DUT is the desired waveform 600, based on the waveform ofthe test signal acquired by the waveform acquisition part 368. Forexample, the test signal correction part 370 corrects the waveform sothat the rising portion 610 is higher than the high-side voltage V_(H),and the falling portion 620 is lower than the low-side voltage V_(L).

By the testing apparatus 30 according to the present embodiment, thetest signal correction part 370 can make the waveform of the test signalapplied to the DUT into the desired waveform by correcting the waveformof the test signal outputted by the driver 324. The testing apparatus 30can thereby apply a test signal to the DUT that has the correct risingportion or falling portion, and can execute high-precision testing.

FIG. 9 shows an example of the structure of the sampler 348. FIG. 9Ashows an example of the structure of the sampler 348 in which fourdiodes are used. The sampler 348 includes a switching circuit havingdiodes 700, 702, 704, and 706, and a capacitor 710. The diodes 700, 702,704, and 706 are turned on by inputting a strobe signal V_(SH) and astrobe signal V_(SL), which is reverse in positive and negative to thestrobe signal V_(SH), to the sampler 348. In this case, since there isno difference in electrical potential between the midpoint of the diode700 and the diode 702, and the midpoint of the diode 704 and the diode706, the electrical potential generated at the midpoint between diode700 and diode 702 by the inputting of the test signal V_(T) is alsogenerated in the midpoint between diode 704 and diode 706, and isapplied to the capacitor 710. Thus, the switching circuit composed of abridge circuit that uses four diodes applies the test signal V_(T) tothe capacitor 710 at a predetermined timing, that is, at the timingindicated by the strobe signal. The comparator 350 compares the voltageapplied to and charged into the capacitor 710 as the sample voltageV_(SMP) with the reference voltage.

FIG. 9B shows an example of the structure of a sampler 348 that uses twodiodes. The sampler 348 is composed of a switching circuit that includesa diode 720 and a diode 722, a resistor 724, a resistor 726, and acapacitor 730. The sampler 348 turns diode 720 and diode 722 on inresponse to the inputting of a strobe signal V_(SH) and a strobe signalV_(SL) which is reverse in positive and negative to the strobe signalV_(SH). In this case, since there is no difference in electricalpotential between the midpoint of diode 720 and diode 722 and themidpoint of resistor 724 and resistor 726, the potential generated inthe midpoint between diode 720 and diode 722 by the inputting of thetest signal V_(T) is also generated in the midpoint between resistor 724and resistor 726, and is applied to the capacitor 730. Thus, theswitching circuit that uses two diodes applies the test signal V_(T) tothe capacitor 730 at a predetermined timing, that is, at the timingindicated by the strobe signal. The comparator 350 compares the voltageapplied to and charged into the capacitor 730 as the sample voltageV_(SMP) with the reference voltage.

FIG. 10 shows a working example of the sampler 348 having noise removalcapability. Strobe signals V_(SL) and V_(SH) having a narrow pulse widthand a large amplitude are given in the sampler 348. A reflection ordelay of a large-amplitude pulse having a narrow width caused byimpedance-mismatched part or the like on the transmission channelproduces a noise. Noise arrives immediately after the strobe signalsV_(SH) and V_(SL). The diodes 700, 702, 704, and 706 constituting theswitching circuit have already returned to the OFF state immediatelyafter the strobe signals V_(SH) and V_(SL), but when noise is appliedthrough the capacitors C1 and C1′, this noise leaks out through thejunction capacitance of the diodes 704 and 706 in the OFF state, theleaked noise arrives at a hold capacitor 710, and the sample voltageV_(SMP) is caused to fluctuate.

In the present invention, a noise extraction circuit 900 is providedadjacent to the sampler 348 in order to remove the noise NOISsuperimposed on the sample voltage V_(SMP). In the working example shownin FIG. 10, the noise extraction circuit 900 is composed of a pair ofdiodes 901 and 902 connected in series and maintained in the OFF stateby direct-current bias voltages, capacitors C2 and C2′ for applying thestrobe signals V_(SL) and V_(SH) to one and the other ends of the seriesconnection, and an extraction line 903 for extracting noise from thejunction of the diodes 901 and 902. Alternatively, as shown in FIG. 15,the noise extraction circuit 900 may be composed of a series circuit ofresistors 911 and 912 instead of the diodes 901 and 902, each having aresistance value equal to the resistance value of the diodes 901 and 902when OFF; capacitors C2 and C2′ for applying the strobe signals V_(SL)and V_(SH) to one and the other ends of this series circuit; and anextraction line 903 for extracting noise from the junction of theresistors 911 and 912.

By the noise extraction circuit 900 shown in FIG. 10, when the strobesignals V_(SL) and V_(SH) are applied through the capacitors C2 and C2′to one and the other ends of the series circuit composed of the diodes901 and 902 maintained in the OFF state, since the strobe signals V_(SL)and V_(SH) are mostly reverse in polarity to each other, the strobesignals cancel out each other, and do not appear in the extraction line903. In contrast, there is no assurance that the component of the noiseNOIS on the capacitor C2 side has a perfectly opposite polarity withrespect to the component thereof on the capacitor C2′ side. Therefore,components having a phase difference appear in the extraction line 903and are extracted as noise. (The noise NOIS superimposed on the samplevoltage V_(SMP) also occurs in this manner.)

The noise NOIS superimposed on the sample voltage V_(SMP) can be removedby inputting the noise NOIS extracted in this manner to one of the inputterminals of an analog subtracter 910 composed of a differentialamplifier, for example, and inputting the sample voltage V_(SMP) to theother input terminal.

FIG. 11 shows the manner in which noise is removed. FIG. 11A shows thestrobe signal, and in this example, the waveforms of V_(SH) and thenoise NOIS. FIG. 11B shows the sample voltage V_(SMP) and the noise NOISsuperimposed thereon. FIG. 11C shows the noise NOIS extracted from thenoise extraction circuit 900. FIG. 11D shows the waveform of the outputsignal of one output terminal d of the differential amplifierconstituting the analog subtracter 910; and FIG. 11E shows the waveformof the output signal of the other output terminal e. As is apparent fromthese waveforms, the noise NOIS can be removed on the output side of theanalog subtracter 910, and the occurrence of error can be minimized inthe comparison with the reference voltage in the comparator.

FIG. 12 shows a working example in which noise removal capability isadded to the sampler 348 shown in FIG. 9B. In other words, this diagramshows a case in which the series circuit of the resistors 724 and 726 isconnected in parallel to the switching circuit composed of the diodes720 and 722, and the sample voltage V_(SMP) is outputted from thejunction of the resistors 724 and 726. The noise NOIS is superimposed onthe sample voltage V_(SMP) of the sampler 348 in the same way as in FIG.10. Since the noise extraction circuit 900 is also the same as the onein FIG. 10, the operation and effects of the circuit shown in FIG. 12are the same as those of the circuit shown in FIG. 10. However, theresistance values selected for the resistors 724 and 726 are about equalto the resistance values of the diodes 720 and 722 when in OFF state.

FIG. 13 shows yet another working example of the sampler 348 havingnoise removal capability. In the working example shown in FIG. 13, thebias voltage sources for the sampler 348 are separated from the biasvoltage sources for the noise extraction circuit 900, and a case isshown in this example in which the voltage of the bias voltage sources+V_(C) and −V_(C) for the noise extraction circuit 900 can be adjusted.By this configuration, the bias voltage sources +V_(C) and −V_(C) of thenoise extraction circuit 900 are separated from the bias voltage sources+V_(B) and −V_(B) of the sampler 348, and the voltages thereof are madeadjustable, whereby the reverse bias voltages applied to the diodes 901and 902 constituting the noise extraction circuit 900 can beindependently adjusted. As a result, the junction capacitance of eachdiodes 901 and 902 can be freely adjusted, and the amplitude of theextracted noise NOIS can be adjusted. As a result, effects are obtainedwhereby the amplitude of the extracted noise NOIS can be matched withthe amplitude of the noise NOIS superimposed on the sample voltageV_(SMP), and the degree of noise NOIS removal can be increased.

FIG. 14 shows a case in which the sampler 348 is structured like thesampler shown in FIG. 9B. The bias voltage sources +V_(C) and −V_(C) ofthe noise extraction circuit 900 are also independently adjustable inthis case, and the amplitude of the extracted noise is also adjustable.

FIG. 15 shows a case in which the bias voltage sources +V_(B) and −V_(B)of the sampler 348 are adjustable, the reverse bias voltages applied tothe four diodes 700, 702, 704, and 706 constituting the switchingcircuit are adjusted, the amplitude of the noise NOIS superimposed onthe sample voltage V_(SMP) is adjusted and matched with the amplitude ofthe noise NOIS extracted from the noise extraction circuit 900 toenhance the degree of noise removal. In the working example shown inFIG. 15, a case is shown in which resistors 911 and 912 havingresistance values equal to the resistance values of the diodes 901 and902 when in OFF state are used in the noise extraction circuit 900instead of the diodes 901 and 902 controlled to the OFF state by areverse bias voltage. Even when this configuration is adopted, the noiseNOIS that arises immediately after application of the strobe signalsV_(SL) and V_(SH) can be extracted in the extraction line 903, and thenoise NOIS superimposed on the sample voltage V_(SMP) can be removedusing the extracted noise NOIS.

FIG. 16 shows a case in which the switching circuit of the sampler 348is composed of diodes 720 and 722, and resistors 724 and 726; the biasvoltage sources +V_(B) and −V_(B) applied to the diodes 720 and 722 areadjustable voltage sources; and the noise extraction circuit 900 isconstructed such that micro-capacity capacitors 921 and 922 having aboutthe same capacitance as the junction capacitance of the diodes areconnected in parallel to the resistors 911 and 912.

The configuration of the sampler 348 is as described in FIG. 14, and isthe same as described in FIGS. 14 and 15 in that the reverse biasvoltage sources +V_(B) and −V_(B) applied to the diodes 720 and 722 areadjustable voltage sources; the amplitude is matched with that of thenoise extracted by the noise extraction circuit 900 to enhance thedegree of noise removal. A characteristic feature in FIG. 16 is that theresistors 911 and 912 used instead of the diodes 901 and 902 in thenoise extraction circuit 900 are connected in parallel to the capacitors921 and 922, respectively. The response characteristics of the noiseextraction circuit 900 can be enhanced by selecting an appropriate valuefor the capacity of the capacitors 921 and 922 according to thefrequency characteristics of the noise. The degree of noise removal canbe even further enhanced by enhancing the response characteristics.

FIG. 17 shows an example of the comparator 350. The comparator 350 iscomposed of a current source 800, a sample voltage transistor 810, areference voltage transistor 820, and a comparison result output part830. The current source 800 generates electric currents on the emittersides of the sample voltage transistor 810 and reference voltagetransistor 820. Upon application of the sample voltage V_(SMP) to thebase, the sample voltage transistor 810 generates at its collector avoltage V_(AREF) as a result of amplification of the sample voltageV_(SMP). Upon application of the reference voltage V_(REF) to the base,the reference voltage transistor 820 generates at its collector avoltage V_(AREF) as a result of amplification of the reference voltageV_(REF). The comparison result output part 830 compares the amplifiedsample voltage V_(ASMP) with the amplified reference voltage V_(AREF),and outputs a comparison result indicating whether the amplified samplevoltage V_(ASMP) is higher than the amplified reference voltage V_(AREF)or not.

Instead of a comparator circuit composed solely of a comparator, thecalibration apparatus 340 according to the present embodiment has acomparator circuit 342 composed of a comparator 350 and a sampler 348that includes a high-speed switching circuit and capacitors. By thisconfiguration, the effects of equivalent rise time due to bandwidthinadequacy of the comparator, the effects of fluctuations in theresponse time of the comparator according to the overdrive voltage, orother effects which decrease the precision of the comparison of thereference voltage with the voltage of the test signal can be prevented,and more accurate calibration can be performed.

FIG. 18 shows an example of the structure of the calibration apparatus340 according to a modification of the first embodiment of the presentinvention. The calibration apparatus 340 has a comparator circuit 342, adetermination part 344, and a timing calibration part 346. Since thecalibration apparatus 340 has substantially the same structure andfunction as the calibration apparatus 340 shown in FIG. 3, descriptionthereof is omitted except for the aspects in which these structures andfunctions differ.

The comparator circuit 342 is composed of a sampler 348 and a comparator350. The sampler 348 samples the test signal at the timing indicated bythe delayed strobe signal, and outputs a sample voltage of the testsignal to the comparator 350. The sampler 348 outputs the referencevoltage V_(REF) as the sample voltage when the switching circuit is OFFby superimposing the reference voltage V_(REF) onto the reverse biasvoltage V_(B) of the diodes in the switching circuit. The comparator 350compares the sample voltage outputted by the sampler 348 with thereference voltage V_(REF), and outputs a comparison result indicatingwhether or not the sample voltage is higher than the reference voltageto the determination part 344.

FIG. 19 shows an example of the sample voltage in the calibrationapparatus 340 according to a modification of the first embodiment of thepresent invention. FIG. 19A shows an example of the waveform of the testsignal inputted to the sampler 348. FIG. 19B shows an example of thewaveform that is the composite of the waveforms of strobe signalsgenerated at different timings. FIG. 19C shows an example of the samplevoltage that corresponds to each of the strobe signals generated atdifferent timings.

When the switching circuit in the sampler 348 is in the OFF state, thesampler 348 outputs the reference voltage V_(REF) as the sample voltage.The sampler 348 outputs a sample voltage that is below the referencevoltage V_(REF) when the test signal is sampled at the timing indicatedby the strobe signal 1000. When the test signal is sampled at the timingindicated by the strobe signal 1010, the sampler 348 outputs a samplevoltage that matches the reference voltage V_(REF). The sampler 348outputs a sample voltage that is above the reference voltage V_(REF)when the test signal is sampled at the timing indicated by the strobesignal 1020. The comparator 350 determines whether the sample voltage ofthe test signal in the timing indicated by the strobe signal is high orlow with respect to the reference voltage V_(REF) according to whetherthe pulse is generated in the positive or negative direction from theperspective of the reference voltage V_(REF) in the sample voltage.

By the calibration apparatus 340 according to the present modification,the comparator 350 can determine comparison of the sample voltage andthe reference voltage according to the direction of the pulse generatedin the sample voltage. The calibration apparatus 340 can thereby reducelinearity error in the comparator 350 and perform calibration withhigher precision.

FIG. 20 shows an example of the overall structure of the testingapparatus 1200 according to a second embodiment of the presentinvention. The testing apparatus 1200 generates a test signal andapplies the test signal to the DUT, compares an expected value with theoutput signal outputted as a result of the operation of the DUT based onthe test signal, and determines the quality of the DUT. An object in thetesting apparatus 1200 according to the present embodiment is toincrease the precision with which the output signal outputted by the DUTis compared with the expected value.

The testing apparatus 1200 is provided with a pattern generator 380, atiming generator 300, a waveform shaper 385, a driver 324, a sampler348, a comparator 350, and a logical comparator 387. The patterngenerator 380 generates a test pattern indicating the pattern of thetest signal applied to the DUT, and an expected value pattern indicatingthe pattern of the expected value with which the output signal outputtedby the DUT is compared. The timing generator 300 generates a timingsignal indicating the timing at which the test signal is applied to theDUT. The timing generator 300 also generates a strobe signal in relationto the timing signal indicating the timing for detecting the outputsignal outputted by the DUT.

The waveform shaper 385 reshapes the waveform of the test signal basedon the test pattern generated by the pattern generator 380 and thetiming indicated by the timing signal generated by the timing generator300, and outputs the result to the driver 324. The driver 324 acquiresthe waveform of the test signal reshaped by the waveform shaper 385, andapplies the test signal to the DUT.

The sampler 348 samples the analog output signal, outputted from the DUTaccording to the test signal applied to the DUT by the driver 324, at apredetermined timing; specifically, at the timing indicated by thestrobe signal outputted by the timing generator 300, and outputs thesample voltage of the output signal to the comparator 350. Thecomparator 350 compares the sample voltage outputted by the sampler 348with an analog reference voltage V_(REF), and outputs to the logicalcomparator 387 a comparison result indicating whether the sample voltageis higher than the reference voltage V_(REF). The logical comparator 387detects the comparison result outputted by the comparator 350 at thetiming indicated by the strobe signal generated by the timing generator300, and determines the quality of the DUT by comparing the comparisonresult thus detected with the expected value pattern generated by thepattern generator 380.

By the testing apparatus 1200 according to the present embodiment, theoutput signal outputted by the DUT is sampled by the sampler 348, andthe sample voltage is compared with the reference voltage by thecomparator 350. By this configuration, the effects of equivalent risetime due to bandwidth inadequacy of the comparator, the effects offluctuations in the response time of the comparator according to theoverdrive voltage, or other effects which decrease precision inreceiving the output signal can be prevented, and more precise testingcan be performed.

The present invention was described above using embodiments, but thetechnological scope of the present invention is not limited by theranges described in the abovementioned embodiments. It is clear to oneskilled in the art that various modifications or improvements can bemade to the abovementioned embodiments. It is also apparent from theclaims that embodiments to which such modifications or improvements areadded may also be included in the technological scope of the presentinvention.

INDUSTRIAL APPLICABILITY

The comparator circuit, calibration apparatus, testing apparatus, andcalibration method according to the present invention are applicable invarious semiconductor manufacturing processes and the like.

1. A comparator circuit that comprises: a sampler having a capacitor, said sampler sampling a measured signal by using a strobe pulse signal and its inversed strobe pulse signal that are both generated at a predetermined timing and applied thereto and outputting a sample voltage having a value of said measured signal at the predetermined timing charged in capacitor; and a comparator for comparing said sample voltage received from the capacitor of the sampler with a reference voltage and outputting a comparison result indicating whether said sample voltage is higher than said reference voltage; wherein said sampler comprises a diode-bridge switching circuit, a strobe pulse applying circuit and a capacitor; said diode-bridge switching circuit comprises an input side pair of diodes and an output side pair of diodes; the input side pair of diodes are connected in series with an input terminal at a junction therebetween to which the measured signal is applied; the output side pair of diodes are connected in series with an output terminal at a junction therebetween to which the capacitor is connected; a series connection of the input side pair of diodes and a series connection of the output side pair of diodes are connected in parallel between first and second terminals to which a reverse bias voltage is supplied so that the diode bridge switching circuit is normally maintained in an OFF state; and the strobe pulse signal applying circuit applies the strobe pulse signal and the inversed strobe pulse signal to the first and second terminals to render the diode bridge switching circuit in an ON state so that a value at the predetermined timing of the measured signal applied to the input terminal is derived from the output terminal and charged in the capacitor as a sample voltage of the measured signal.
 2. A comparator circuit that comprises a sampler having a capacitor, said sampler sampling a measured signal by using a strobe pulse signal and its inversed strobe pulse signal that are both generated at a predetermined timing and applied thereto and outputting a sample voltage having a value of said measured signal at the predetermined timing charged in the capacitor; a comparator for comparing said sample voltage received from the capacitor of the sampler with a reference voltage and outputting a comparison result indicating whether said sample voltage is higher than said reference voltage; a noise extraction circuit for extracting noise components superimposed on the sample voltage that follow the strobe pulse signal and the inversed strobe pulse signal; and an analog subtraction circuit for performing analog subtraction of the noise components extracted by the noise extraction circuit from the sample voltage so that the noise components superimposed on said sample voltage are removed and the comparator compares the resulting sample voltage with the reference voltage.
 3. The comparator circuit according to claim 2, wherein said noise extraction circuit comprises a series connection of a pair of diodes for the noise extraction circuit with an output terminal at a junction therebetween and maintained in the OFF state by a reverse bias voltage applied to the series connection of the pair of diodes; and an extraction line connected to the output terminal, wherein a strobe pulse signal applying circuit applies the strobe pulse signal and the inversed strobe pulse signal to the pair of diodes; and the noise components are extracted from the output terminal to the extraction line.
 4. The comparator circuit according to claim 2, wherein said noise extraction circuit comprises a pair of resistors connected in series with an output terminal at a junction therebetween and each having a resistance value equivalent to an OFF resistance value of one of the diodes; and an extraction line connected to the output terminal, wherein a strobe pulse signal applying circuit applies the strobe pulse signal and the inversed strobe pulse signal to the pair of resistors; and the noise components are extracted from the output terminal to the extraction line.
 5. The comparator circuit according to any one of claims 2 through 4 that comprises a voltage adjusting means for varying the reverse bias voltage applied to the noise extraction circuit to adjust the amplitude of the noise components extracted via said extraction line.
 6. The comparator circuit according to claim 4, wherein a capacitor having a capacitance equivalent to the junction capacitance of the diodes is connected in parallel to each of the pair of series-connected resistors constituting said noise extraction circuit.
 7. The comparator circuit according to any one of claims 1 through 4, wherein said comparator comprises: a sample voltage transistor for amplifying said sample voltage; a reference voltage transistor for amplifying said reference voltage; and a comparison result output part for comparing said amplified sample voltage with said amplified reference voltage and outputting a comparison result indicating whether said amplified sample voltage is higher than said amplified reference voltage.
 8. A calibration apparatus for acquiring a measured signal outputted by a driver and calibrating the output timing of said measured signal from said driver, said calibration apparatus comprising: a sampler for sampling said measured signal at a predetermined timing and outputting the sample voltage of said measured signal; a comparator for comparing said sample voltage with a reference voltage and outputting a comparison result indicating whether said sample voltage is higher than said reference voltage; a determination part for determining that said sample voltage matches said reference voltage at a timing at which said comparison result changes as said timing of sampling is varied by said sampler; and a timing calibration part for calibrating the output timing of said measured signal from said driver based on said timing at which it is determined in said determination part that said sample voltage matches said reference voltage.
 9. A testing apparatus for testing a device under test; said testing apparatus comprising: a timing generator for generating a timing signal that indicates timing at which a test signal is applied to each of a plurality of terminals provided to said device under test; a plurality of timing delay units for delaying said timing signals; a plurality of drivers provided so as to correspond with each of said plurality of timing delay units, for applying said test signal to each of said plurality of terminals at the timing indicated by each of said timing signals delayed by each of said plurality of timing delay units; a sampler for sampling said test signal outputted, at a predetermined timing, by the corresponding driver for each of said plurality of drivers, and outputting the sample voltage of said test signal; a comparator for comparing said sample voltage with a reference voltage and outputting a comparison result indicating whether said sample voltage is higher than said reference voltage; a determination part for determining that said sample voltage matches said reference voltage at a timing at which said comparison result changes as said timing of sampling is varied by said sampler; and a timing calibration part for calibrating the delay time caused in said timing signal by at least one of said plurality of timing delay units based on said timing at which it is determined in said determination part that said sample voltage matches said reference voltage for each of said plurality of drivers, in order to synchronize the timing at which said rest signal outputted by each of said plurality of drivers is applied to the device under test.
 10. The testing apparatus according to claim 9, wherein said timing generator also generates a strobe signal in relation to said timing signal, for indicating said dining at which said sampler performs sampling, and the timing at which said determination part detects said comparison results.
 11. The testing apparatus according to claim 10, further comprising: a frequency divider for frequency-dividing said strobe signal; and a strobe delay unit for delaying said strobe signal frequency-divided in said frequency divider; wherein said determination part determines that said sample voltage matches said reference voltage in said delay time by which said comparison result is changed when a change is induced in the delay time by which said strobe delay unit delays said strobe signal; and said timing calibration part calibrates the delay time caused in said timing signal by at least one of said plurality of timing delay units based on the delay time of said strobe signal at which it is determined in said determination part that said sample voltage matches said reference voltage for each of said plurality of drivers, in order to synchronize the timing at which said rest signal outputted by each of said plurality of drivers is applied to the device under test.
 12. The testing apparatus according to claim 11, further comprising: a reference voltage controller for changing said reference voltage with which said comparator compares said sample voltage of said test signal, in order to acquire a voltage at the timing indicated by said delayed strobe signal in said test signal outputted by each of said plurality of drivers; a waveform acquisition part for acquiring the waveform of said test signal outputted by each of said plurality of drivers, by changing the delay time for delaying said strobe signal by said strobe delay unit, and by changing said reference voltage by said reference voltage controller; and a test signal correction part for correcting the signal outputted by the corresponding driver so that the desired said test signal is applied to said device under test based on the waveform of said test signal outputted by each of said plurality of drivers acquired by said waveform acquisition part.
 13. A calibration method for acquiring a test signal outputted by each of a plurality of drivers provided in a testing apparatus for testing a device under test and calibrating the output timing of said test signal from each of said plurality of drivers; said calibration method comprising: a timing generation step for generating a timing signal that indicates timing at which said test signal is applied to each of a plurality of terminals of said device under test; a timing delay step for delaying said timing signals and outputting a plurality of delayed timing signals; a test signal outputting step whereby said plurality of drivers each output said test signal at the timing indicated by each of said plurality of delayed timing signals; a sampling step for sampling at a predetermined timing said test signal outputted by the corresponding driver and outputting the sample voltage of said test signal for each of said plurality of drivers; a comparison step for comparing said sample voltage with a reference voltage and outputting a comparison result indicating whether said sample voltage is higher than said reference voltage; a determination step for determining that said sample voltage matches said reference voltage when said comparison result changes as said timing at which said test signal is sampled in said sampling step is changed; and a timing calibration step for calibrating the delay time caused in said timing signal by at least one of said plurality of timing delay units provided so as to correspond to each of said plurality of drivers, based on said timing at which it is determined in said determination step that said sample voltage matches said reference voltage for each of said plurality of drivers, in order to synchronize the timing at which said test signal outputted by each of said plurality of drivers is applied to the device under test.
 14. The comparator circuit according to claim 5, wherein said comparator comprises: a sample voltage transistor for amplifying said sample voltage; a reference voltage transistor for amplifying said reference voltage; and a comparison result output part for comparing said amplified sample voltage with said amplified reference voltage and outputting a comparison result indicating whether said amplified sample voltage is higher than said amplified reference voltage.
 15. The comparator circuit according to claim 6, wherein said comparator comprises: a sample voltage transistor for amplifying said sample voltage; a reference voltage transistor for amplifying said reference voltage; and a comparison result output part for comparing said amplified sample voltage with said amplified reference voltage and outputting a comparison result indicating whether said amplified sample voltage is higher than said amplified reference voltage.
 16. A comparator circuit comprising: a sampler that comprises a diode bridge switching circuit, and a strobe pulse signal applying circuit; and a comparator; wherein the diode bridge switching circuit supplied with the measured signal at an input terminal thereof is normally maintained in an OFF state by a reverse bias voltage supplied thereto and rendered in an ON state by a strobe pulse signal and its inversed strobe pulse signal, which are both generated at a predetermined timing and applied thereto from a strobe pulse signal applying circuit, and outputs at an output terminal thereof a sample voltage having a value of the measured signal at the predetermined timing; and the comparator compares the sample voltage outputted from the sampler with a reference voltage and outputs a comparison result indicating whether the sample voltage is higher than the reference voltage.
 17. A comparator circuit that comprises: a sampler having a capacitor, said sampler sampling a measured signal by using a strobe pulse signal and its inversed strobe pulse signal that are both generated at a predetermined timing and applied thereto and outputting a sample voltage having a value of said measured signal at the predetermined timing charged in the capacitor; and a comparator for comparing said sample voltage received from the capacitor of the sampler with a reference voltage and outputting a comparison result indicating whether said sample voltage is higher than said reference volume; wherein: the sampler comprises a diode bridge switching circuit, a strobe pulse signal applying circuit, and a capacitor, the diode bridge switching circuit comprises an input side pair of diodes, and an output side pair of resistors; the input side pair of diodes are connected in series with an input terminal at a junction therebetween to which the measured signal is applied; the output side pair of resistors are connected in series with an output terminal at a junction therebetween to which the capacitor is connected; a series connection of the input side pair of diodes and a series connection of the output side pair of resistors are connected in parallel between first and second terminals to which a reverse bias voltage is supplied so that the diode bridge switching circuit is normally maintained in an OFF state; and the strobe pulse signal applying circuit applies the strobe pulse signal and the inversed strobe pulse signal to the first and second terminals to render the diode bridge switching circuit in an ON state so that a value at the predetermined timing of the measured signal applied to the input terminal is derived from the output terminal and charged in the capacitor as a sample voltage of the measured signal.
 18. The comparator circuit according to claim 1 or 17, wherein the sampler comprises a voltage adjusting means far varying the reverse bias voltage applied to the diode bridge switching circuit to adjust the amplitude of noise components superimposed on the sample voltage. 